1. Field of the Invention
The present invention relates to a method for growing a p-type silicon single crystal for silicon wafers used as semiconductor materials, more particularly to a method for growing a silicon single crystal with excellent yield which makes it possible to obtain a larger number of silicon wafers with a required resistivity value in the longitudinal direction of a rod-like single crystal.
2. Description of the Prior Art
When a silicon single crystal having a desired resistivity is grown by the Czochralski method, a segregation coefficient inherent to the substance and determined by the type of silicon and additives has to be taken into account. Because the resistivity typically decreases toward the rear part of the single-crystal ingot that has been pulled, when the desired resistivity range is comparatively narrow, there are portions of the ingot with a resistivity outside this desired range and those portions cannot be used as products.
Various methods for adding n-type impurities have been suggested as methods for eliminating the effect of p-type impurities such as boron and increasing the apparent segregation coefficient (Japanese Patent Application Laid-open No. H10-29894, Japanese Patents No. 2804456, 2804455, 2756476). With those methods a large number of wafers with a desired resistivity value can be obtained from a single ingot and the yield can be increased.
With the process for adjusting the resistivity of a single-crystal silicon described in Japanese Patent Application Laid-open No. H10-29894, it is necessary to introduce an additive for suppressing the decrease in resistivity into the bottom portion of a quartz crucible. However, this additive should not be melted during initial melting and a complex method has to be employed for actual implementation of the process. Furthermore, because an additive has to be added to the melt in the course of the crystal growth, certain special tools are required and the process becomes complex.
With the methods described in Japanese Patents No. 2804456 and 2804455, an element (Ga, Sb, or In) capable of decreasing the thermal expansion coefficient in the vicinity of a melting point is added to a Si melt having B or P added thereto, or an element (B or P) capable of increasing the thermal expansion coefficient in the vicinity of a melting point is added to a Si melt having Ga or Sb added thereto and the melt is then pulled, thereby making it possible to grow a single crystal with uniform distribution of impurities in the growth direction.
With the method described in Japanese Patent No. 2756476, the amount of impurities to be added is found with a special computational formula and the amount thus found is added to improve the uniformity of resistivity value in the wafer surface obtained by growing by a CZ or FZ method. However, when pulling is conducted at a high rate upon addition of n-type impurities by the aforementioned method, a portion in which the resistivity value makes a transition from decrease to increase and is inverted sometimes appears in the vicinity of the ingot bottom. Therefore, the required resistivity value of the ingot is difficult to ensure, resistivity values of all the wafers have to be measured in the wafer production process, and the process flow often becomes difficult.